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4.9 Low Battery Configuration Registers (LBCFG)
Page 0x01, 0x05 - LBCFG05 [default 0xB1]
Name
Bits
R/W
Description
Do not change default bit pattern:
Reserved
7,6,5,4
r/w
1011 → default bit pattern
Low battery detection enable:
LB_En
3
r/w
0 → Detection off
1 → Detection on
Low battery detection threshold:
000 → 1.79 V
001 → 1.84 V
010 → 1.90 V
LB_Thres
2,1,0
r/w
011 → 1.97 V
100 → 2.02 V
101 → 2.08 V
110 → 2.14 V
111 → 2.20 V
Table 47
Page 0x01, 0x06 - LBCFG06 [default 0x96]
Name
Bits
R/W
Description
Low battery status:
LB_Status
7
r
0 → battery voltage below threshold
1 → battery voltage above threshold
Map low battery detect to pin 24:
LB_Out
6
r/w
0 → not mapped
1 → mapped
Reserved
5,4,3,
2,1,0
r/w
Do not change default bit pattern:
010110 → default bit pattern
Table 48
Note: take care to immediately return to configuration register memory map page 0 following a read or write to
the low battery configuration registers in page 1. Page configuration register PGCFG1F is mapped into all pages
at the same address of 0x1F. Bits 0..1 of this register control page selection. See Table 46.
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Page 41 of 67
TRC105 - 05/29/13
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